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73M1903 Modem Analog Front End
Simplifying System IntegrationTM
DATA SHEET
February 2009
DESCRIPTION The Teridian 73M1903 Analog Front End (AFE) IC includes fully differential hybrid driver outputs, which connect to the telephone line interface through a transformer-based DAA. The receive pins are also fully differential for maximum flexibility and performance. This arrangement allows for the design of a high performance hybrid circuit to improve signal to noise performance under low receive level conditions, and compatibility with any standard transformer intended for PSTN communications applications. The device incorporates a programmable sample rate circuit to support soft modem and DSP based implementations of all speeds up to V.92 (56 kbps). The sampling rates supported are from 7.2 kHz to 14.4 kHz by programming pre-scaler NCO and PLL NCO. The 73M1903 device incorporates a digital host interface that is compatible with the serial ports found on most commercially available DSPs and processors and exchanges both payload and control information with the host. Cost-saving features of the device include an input reference frequency circuit, which accepts a range of crystals from 9-27 MHz. It also accepts external reference clock values between 9-40 MHz generated by the host processor. In most applications, this eliminates the need for a dedicated crystal oscillator and reduces the bill of material (BOM). The 73M1903 also supports two analog loop back and one digital loop back test modes.
VBG (HYBRID) TXAP TXAN
FEATURES * * * * * * * * * * * * * * * Up to 56 kbps (V.92) performance Programmable sample rates (7.2 - 14.4 kHz) Reference clock range of 9-40 MHz Crystal frequency range of 9-27 MHz Host synchronous serial interface operation Pin compatible with 73M2901CL/CE modems Low power modes On board line interface drivers Fully differential receiver and transmitter Drivers for transformer interface 3.0 V - 3.6 V operation 5 V tolerant I/O Industrial temperature range (-40 to +85 C) JATE compliant transmit spectrum Package options: * 32-pin QFN * 20-pin TSSOP RoHS compliant (6/6) lead-free packages
*
APPLICATIONS * * * * * * * * * *
SCLK SDIN
Set Top Boxes Personal Video Recorders (PVR) Multifunction Peripherals (MFP) Fax Machines Internet Appliances Game Consoles Point of Sale Terminals Automatic Teller Machines Speaker Phones RF Modems
Transmit Drivers/ Filters Receive Mux/ Filters DAA Controls
Analog Sigma Delta
Ref.
RXAP RXAN
DAC
Control Registers
Serial Port
SDOUT FSB
GPIO HOOK
Clocks
Control Logic
Crystal
Rev. 2.0
(c) 2009 Teridian Semiconductor Corporation
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73M1903 Data Sheet
DS_1903_032
Table of Contents
Signal Description ................................................................................................................................. 4 1.1 Serial Interface ............................................................................................................................. 5 2 Control and Status Registers ................................................................................................................ 8 2.1 GPIO .......................................................................................................................................... 10 2.1.1 GPIO Data (GPIO): Address 02h.................................................................................. 10 2.1.2 GPIO Direction (DIR): Address 03h .............................................................................. 10 2.2 Analog I/O .................................................................................................................................. 10 2.2.1 Control Register (CTRL 11): Address 0Bh .................................................................... 11 2.2.2 Control Register (CTRL 12): Address 0Ch .................................................................... 11 2.2.3 Control Register (CTRL 13): Address 0Dh .................................................................... 12 2.2.4 Control Register (CTRL 14): Address 0Eh .................................................................... 12 3 Clock Generation ................................................................................................................................ 13 3.1 Crystal Oscillator and Pre-scaler NCO ...................................................................................... 13 3.1.1 Control Register (CTRL 8): Address 08h....................................................................... 13 3.1.2 Control Register (CTRL 9): Address 09h....................................................................... 13 3.1.3 Control Register (CTRL 10): Address 0Ah .................................................................... 13 4 Modem Receiver ................................................................................................................................. 18 5 Modem Transmitter ............................................................................................................................. 21 5.1 Transmit Levels .......................................................................................................................... 22 5.2 Transmit Power - dBm ............................................................................................................... 23 5.3 Control Register (CTRL1): Address 00h ................................................................................... 23 5.4 Control Register (CTRL2): Address 01h ................................................................................... 24 5.5 Revision Register: Address 06h ................................................................................................ 24 6 Test Modes ......................................................................................................................................... 25 7 Power Saving Modes .......................................................................................................................... 25 8 Electrical Specifications ...................................................................................................................... 26 8.1 Absolute Maximum Ratings ....................................................................................................... 26 8.2 Recommended Operating Conditions........................................................................................ 26 8.3 Digital Specifications .................................................................................................................. 27 8.3.1 DC Characteristics ......................................................................................................... 27 8.3.2 AC Timing ...................................................................................................................... 28 8.4 Analog Specifications................................................................................................................. 29 8.4.1 DC Specifications .......................................................................................................... 29 8.4.2 AC Specifications ........................................................................................................... 29 8.5 Performance .............................................................................................................................. 30 8.5.1 Receiver ......................................................................................................................... 30 8.5.2 Transmitter ..................................................................................................................... 31 9 Pinouts ................................................................................................................................................ 33 9.1 32-Pin QFN Pinout ..................................................................................................................... 33 9.2 20-Pin TSSOP Pinout ................................................................................................................ 34 10 Mechanical Specifications................................................................................................................... 35 10.1 32-Pin QFN Mechanical Drawings ............................................................................................. 35 10.2 20-Pin TSSOP Mechanical Drawings ........................................................................................ 36 11 Ordering Information ........................................................................................................................... 37 Appendix A - 73M1903 DAA Resistor Calculation Guide .......................................................................... 38 Appendix B - Crystal Oscillator .................................................................................................................. 41 Revision History .......................................................................................................................................... 46 1
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73M1903 Data Sheet
Figures
Figure 1: SCLK and FS with SckMode = 0 ................................................................................................... 7 Figure 2: Control Frame Position versus SPOS ........................................................................................... 7 Figure 3: Serial Port Timing Diagram............................................................................................................ 9 Figure 4: Analog Block Diagram ................................................................................................................. 11 Figure 5: Clock Generation ......................................................................................................................... 17 Figure 6: Overall Receiver Frequency Response ....................................................................................... 19 Figure 7: Rx Passband Response .............................................................................................................. 19 Figure 8: RXD Spectrum of 1 kHz Tone ..................................................................................................... 20 Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes ......... 20 Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal ............................................ 21 Figure 11: Serial Port Data Timing .............................................................................................................. 28 Figure 12: 32-Pin QFN Pinout ..................................................................................................................... 33 Figure 13: 20-Pin TSSOP Pinout ................................................................................................................ 34 Figure 14: 32-Pin QFN Mechanical Specifications ..................................................................................... 35 Figure 15: 20-Pin TSSOP Mechanical Specifications ................................................................................. 36 Figure 15: NCO Block Diagram .................................................................................................................. 41 Figure 16: PLL Block Diagram .................................................................................................................... 42
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ......................................................... 4 Table 2: Memory Map ................................................................................................................................... 8 Table 3: PLL Loop Filter Settings ................................................................................................................ 11 Table 4: Kvco versus Settings at Vc=1.6 V, 25 C...................................................................................... 13 Table 5: PLL Power Down .......................................................................................................................... 14 Table 6: Examples of NCO Settings ........................................................................................................... 14 Table 7: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................... 15 Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz ........................................................ 16 Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz .......................................................... 16 Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz ...................................................... 17 Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz ........................................................ 17 Table 12: Receive Gain............................................................................................................................... 18 Table 13: Peak to RMS Ratios for Various Modulation Types.................................................................... 23 Table 14: Serial I/F Timing .......................................................................................................................... 28 Table 15: Reference Voltage Specifications ............................................................................................... 29 Table 16: Maximum Transmit Levels .......................................................................................................... 29 Table 17: Receiver Performance Specifications ......................................................................................... 30 Table 18: Transmitter Performance Specifications ..................................................................................... 31 Table 19: 32-Pin QFN Pin Definitions ......................................................................................................... 33 Table 20: 20-Pin TSSOP Pin Definitions .................................................................................................... 34
Rev. 2.0
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73M1903 Data Sheet
DS_1903_032
1 Signal Description
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the same pin out. The following table describes the function of each pin. There are two pairs of power supply pins, VPA (analog) and VPD (digital). They should be separately decoupled from the supply source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately isolate and decouple these supplies will compromise device performance. Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles Pin Name VND VNA VPD VPA VPPLL VNPLL RST OSCIN OSCOUT GPIO(0-7) VREF RXAP RXAN TXAP TXAN SCLK SDOUT SDIN FS TYPE SckMode Type GND GND PWR PWR PWR PWR I I O I/O O I I O O O O I O I I 32QFN Pin # 1,22 16 2,25 10 20 17 9 19 18 3, 4, 5, 6, 23, 24,30,31 13 15 14 12 11 8 32 29 7 27 28 20VT Pin# 2,18 13 3 8 17 14 7 16 15 N/A 6 12 11 10 9 5 1 20 4 19 Negative Digital Ground Negative Analog Ground Positive Digital Supply Positive Analog Supply Positive PLL Supply, shared with VPD Negative PLL Ground Master reset. When this pin is a logic 0 all registers are reset to their default states; Weak-pulled high- default. Crystal oscillator input. When providing an external clock source, drive OSCIN. Crystal oscillator circuit output pin. Software definable digital input/output pins. Not available in the 20VT (TSSOP) package. Reference voltage pin (Reflects VREF). Receive analog positive input. Receive analog negative input. Transmit analog positive output. Transmit analog negative output. Serial interface clock. With SCLK continuous selected, Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz) Serial data output (or input to the host). Serial data input (or output from the host). Frame synchronization. (Active Low) Type of frame sync. Open, weak-pulled high = early (mode1); tied low = late (mode0). Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK Continuous; tied low = 32 clocks per R/W cycle. Not available in 20VT. Description
NA
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73M1903 Data Sheet
1.1
Serial Interface
The serial data port is a bi-directional port that can be supported by most DSPs. Although the 73M1903 is a peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that can be programmed by the user. The serial bit clock is always derived by dividing the system clock by 18. The sclk rate, Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions. They are: 1. Fxtal 1 = 27 MHz, Fs 1 = 7.2 kHz 2. Fxtal 2 = 18.432 MHz, Fs 2 = 8 kHz. 3. Fxtal 3 = 24.576 MHz, Fs 3 = 9.6 kHz - chip default. Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal frequency, Fxtal, and therefore the serial bit clock will be Sclk = Fsys/18 = Fxtal/18. Examples: 1. If Fxtal 1 = 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz. 2. If Fxtal 2 = 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz. 3. If Fxtal 3 = 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz. When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the system clock will transition to the PLL-based clock in a glitch-less manner. Examples: 1. If Fs 1 = 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz. 2. If Fs 2 = 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz. 3. If Fs 3 = 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz. This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a designated serial port register - location bit 7, 0Eh. The transition should be forced on or after the second Frame Synch period following the write to a designated PLL programming register (0Dh). When reprogramming the PLL the host should first transition the system clock to the crystal before reprogramming the PLL so that any transients associated with it will not adversely impact the serial port communication. Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h), ENFE=0. During the normal operation, a data FS is generated by the 73M1903 at the rate of Fs. For every data FS there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin programmable for type. FS can either be early or late determined by the state of the TYPE input pin. When the TYPE pin is left open, an early FS is generated in the bit clock prior to the first data bit transmitted or received. When held low, a late FS operates as a chip select; the FS signal is active for all bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines the frame synchronization mode used.
Rev. 2.0
5
73M1903 Data Sheet The bits transmitted on the SDOUT pin are defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
DS_1903_032
Bit1
Bit0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN are defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 TX15 TX14 TX13 TX12 TX11 TX10 TX9 In this case TX0=0 is forced. If the Hardware Control bit (bit 0 of register 01h) is set to one, the 16 bits that are received on the SDIN input are defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 TX15 TX14 TX13 TX12 TX11 TX10 TX9 Bit8 TX8 Bit7 TX7 Bit6 TX6 Bit5 TX5 Bit4 TX4 Bit3 TX3 Bit2 TX2 Bit1 TX1 Bit0 TX0 Bit8 TX8 Bit7 TX7 Bit6 TX6 Bit5 TX5 Bit4 TX4 Bit3 TX3 Bit2 TX2 Bit1 TX1 Bit0 CTL
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data frames. If the hardware control bit is set to zero, CTL is used by software to request a control frame. If CTL is high, a control frame will be initiated before the next data frame. A control frame allows the controller to read or write status and control to the 73M1903. The control word received on the SDIN pin is defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 R/W A6 A5 A4 A3 A2 A1 Bit8 A0 Bit7 D7 Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0
The control word transmitted on the SDOUT pin is defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 0 0 0 0 0 0 0 Bit8 0 Bit7 D7 Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0
If the R/W bit is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data contained in the register pointed to by address bits A6-A0. Only one control frame can occur between any two data frames. Writes to unimplemented registers are ignored. Reading an unimplemented register returns a value of 0. The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is set to a 0 the control frames occur mid way between data frames, i.e., the time between data frames is equal. If SPOS is set to a 1, the control frame is 1/4 of the way between consecutive data frames, i.e., the control frame is closer to the first data frame. This is illustrated in Figure 3. New to the 73M1903 modem AFE IC is a feature that shuts off the serial clock (SCLK) after 32 cycles of SCLK following the frame synch (Figure 2). This feature is unavailable in the 20 TSSOP package option. This mode is controlled by the SckMode pin. If this pin is left open the clock will run continuously. If SckMode is low the clock will be gated on for 32 clocks for each FS. The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN pin is sampled on the falling edge of SCLK. Figure 4 shows the timing diagrams for the serial port. 6 Rev. 2.0
DS_1903_032
73M1903 Data Sheet
32 Cycles of sclk
SCLK
FS(mode1)
SCLK and FS in mode 1
32 Cycles of sclk
SCLK
FS(mode0)
SCLK and FS in mode 0
Figure 1: SCLK and FS with SckMode = 0
Figure 2: Control Frame Position versus SPOS
Rev. 2.0
7
73M1903 Data Sheet
DS_1903_032
2 Control and Status Registers
Table 2 shows the memory map of addressable registers in the 73M1903. Each register and its bits are described in detail in the following sections. Table 2: Memory Map Address Default Bit 7 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0E-7F 08h 00h FFh FFh 00h 00h 10h 00h 00h 0Ah 22h 12h 00h C0h 00h ENFE TMEN GPIO7 DIR7 Bit 6 Unused DIGLB GPIO 6 DIR6 Bit 5 TXBST1 ANALB GPIO 5 DIR5 Bit 4 INTLB GPIO 4 DIR4 Bit 3 Bit 2 RXG1 GPIO 2 DIR2 Bit 1 RXG0 GPIO 1 DIR1 Bit 0 RXGAIN HC GPIO 0 DIR0
TXBST0 TXDIS GPIO 3 DIR3
Reserved RXPULL SPOS
Reserved Reserved Reserved Reserved Rev3 Unused Pseq7 Prst2 Ichp3 Unused Nseq7 Xtal1 Frcvco Unused Rev2 Reserved Pseq6 Prst1 Ichp2 Ndvsr6 Nseq6 Xtal0 PwdnPLL Unused
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Rev1 Pseq5 Prst0 Ichp1 Ndvsr5 Nseq5 Rev0 Pseq4 Pdvsr4 Ichp0 Ndvsr4 Nseq4 Unused Pseq3 Pdvsr3 FL Ndvsr3 Nseq3 Unused Unused Reserved Reserved Reserved Pseq2 Pdvsr2 Kvco2 Ndvsr2 Nseq2 Nrst2 Unused Unused Pseq1 Pdvsr1 Kvco1 Ndvsr1 Nseq1 Nrst1 Unused Unused Pseq0 Pdvsr0 Kvco0 Ndvsr0 Nseq0 Nrst0 Unused Unused Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Unused Reserved Unused Unused Unused
To prevent unintended operation, do not write to reserved or unused locations. These locations are for factory test or future use only and are not intended for customer programming.
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Rev. 2.0
DS_1903_032
73M1903 Data Sheet
SCLK FS(mode1) SDIN SDOUT TX15 RX15 TX14 RX14 TX13 RX13 TX12 RX12 TX11 RX11 TX10 RX10 TX9 RX9 TX8 RX8 TX7 RX7 TX6 RX6 TX5 RX5 TX4 RX4 TX3 RX3 TX2 RX2 TX1 RX1 CTL RX0
Data Frame With Early Frame Sync
SCLK FS(mode1) SDIN SDOUT R/W zero A6 zero A5 zero A4 zero A3 zero A2 zero A1 zero A0 zero DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 DI3 DO3 DI2 DO2 DI1 DO1 DI0 DO0
Control Frame With Early Frame Sync
SCLK FS(mode0) SDIN R/W zero SDOUT Control Frame With Late Frame Sync A6 zero A5 zero A4 zero A3 zero A2 zero A1 zero A0 zero DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 DI3 DO3 DI2 DO2 DI1 DO1 DI0 DO0
7.2KHz (8KHz) SCLK FS SDIN SDOUT
TX RX
TX RX
TX RX Data Frame
TX RX
TX RX
1 RX
R 0
A 0
A 0
A 0
DI DO
DI DO
DI DO
TX RX
TX RX
TX RX Data Frame
TX RX
TX RX
0 RX
Control Frame
Relation Between the Data and Control Frames
Figure 3: Serial Port Timing Diagram
Rev. 2.0
9
73M1903 Data Sheet
DS_1903_032
2.1
GPIO
The 73M1903 modem AFE device provides 8 user defined I/O pins. Each pin is programmed separately as either an input or an output by a bit in a direction register. If the bit in the direction register is set high, the corresponding pin is an input whose value is read from the GPIO data register. If it is low, the pin will be treated as an output whose value is set by the GPIO data register. To avoid unwanted current contention and consumption in the system from the GPIO port before the GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins. The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.
2.1.1
Bit 7 GPIO7
GPIO Data (GPIO): Address 02h
Bit 6 GPIO6 Bit 5 GPIO5 Bit 4 GPIO4 Bit 3 GPIO3 Bit 2 GPIO2 Bit 1 GPIO1 Bit 0 GPIO0
Reset State FFh
Bits in this register will be asserted on the GPIO(7:0) pins if the corresponding direction register bit is a 0. Reading this address will return data reflecting the values of pins GPIO(7:0).
2.1.2
Bit 7 DIR7
GPIO Direction (DIR): Address 03h
Bit 6 DIR6 Bit 5 DIR5 Bit 4 DIR4 Bit 3 DIR3 Bit 2 DIR2 Bit 1 DIR1 Bit 0 DIR0
Reset State FFh
This register is used to designate the GPIO pins as either inputs or outputs. If the register bit is low, the corresponding GPIO pin is programmed as an output. If the register bit is a 1, the corresponding pin will be treated as an input.
2.2
Analog I/O
Figure 4 shows the block diagram of the analog front end. The analog interface circuit uses differential transmit and receive signals to and from the external circuitry. The hybrid driver in the 73M1903 IC is capable of connecting directly, but not limited to, a transformerbased Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA's line coupling transformer, which carries an impedance on the primary side that is typically rated at 600 , depending on the transformer and matching network. The hybrid drivers can also drive high impedance loads without modification. The class AB behavior of the amplifiers provides load dependent power consumption. An on-chip band gap voltage is used to provide an internal voltage reference and bias currents for the analog receive and transmit channels. The reference derived from the bandgap, nominally 1.25 Volts, is multiplied to 1.36 Volts and output at the VREF pin. Several voltage references, nominally 1.25 Volts, are used in the analog circuits. The band gap and reference circuits are disabled after a chip reset since the ENFE bit is reset to a default state of zero. When ENFE=0, the band gap voltage and the analog bias currents are disabled. In this case all of the analog circuits are powered down and draw less than 5 A of current. A clock generator (CKGN) is used to create all of the non-overlapping phase clocks needed for the time sampled switched-capacitor circuits, ASDM, DAC1, and TLPF. The CKGN input is two times the analog/digital interface sample rate or 3.072 MHz clock for Fs=8 kHz.
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73M1903 Data Sheet
Figure 4: Analog Block Diagram Table 3: PLL Loop Filter Settings FL 0 1 PLLloop Filter Settings R1=32 k,C1=100 pF,C2=2.5 pF R1=16 k, C1=100 pF,C2=2.5 pF
2.2.1
Bit 7
Control Register (CTRL 11): Address 0Bh
Bit 6 Ndvsr6 Bit 5 Ndvsr5 Bit 4 Ndvsr4 Bit 3 Ndvsr3 Bit 2 Ndvsr2 Bit 1 Ndvsr1 Bit 0 Ndvsr0
Reset State 12h
Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored.
2.2.2
Bit 7 Nseq7
Control Register (CTRL 12): Address 0Ch
Bit 6 Nseq6 Bit 5 Nseq5 Bit 4 Nseq4 Bit 3 Nseq3 Bit 2 Nseq2 Bit 1 Nseq1 Bit 0 Nseq0
Reset State 00h
Nseq[7:0] represents the divisor sequence. Rev. 2.0 11
73M1903 Data Sheet
DS_1903_032
2.2.3
Bit 7 Xtal1
Control Register (CTRL 13): Address 0Dh
Bit 6 Xtal0 Bit 5 Bit 4 Bit 3 Bit 2 Nrst2 Bit 1 Nrst1 Bit 0 Nrst0
Reset State 48h Reserved Reserved Unused
Xtal[1:0] :
00 = Xtal osc. bias current at 120 A 01 = Xtal osc. bias current at 180 A 10 = Xtal osc. bias current at 270 A 11 = Xtal osc. bias current at 450 A
If OSCIN is used as a Clock input, "00" setting should be used to save power(=167 A at 27.648 MHz). Nrst[3:0] represents the rate at which the NCO sequence register is reset. The address 0Dh must be the last register to be written to when effecting a change in PLL.
2.2.4
Bit 7 Frcvco
Control Register (CTRL 14): Address 0Eh
Bit 6 Bit 5 Bit 4 Bit 3 Unused Bit 2 Unused Bit 1 Unused Bit 0 Unused
Reset State 00h PwdnPLL Reserved Unused
Frcvco = 1 forces VCO as system clock. This is reset upon RST, PwdnPLL = 1 or ENFE = 0. Both PwdnPLL and ENFE are delayed coming out of digital section to keep PLL alive long enough to transition the system clock to crystal clock when Frcvco is reset by PwdnPLL or ENFE. PwdnPll = 1 forces Power down of PLL analog section.
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73M1903 Data Sheet
3 Clock Generation
3.1 Crystal Oscillator and Pre-scaler NCO
The crystal oscillator operates over wide choice of crystals (from 9 MHz to 27 MHz) and it is first input to an NCO based pre-scaler (divider) prior to being passed onto an on-chip PLL. The intent of the prescaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference frequency, Fref, for the PLL. The NCO pre-scaler requires a set of three numbers to be entered through the serial port (Pseq[7:0], Prst[2:0] and Pdvsr[2:0]. The PLL also requires 3 numbers as for programming; Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers that control the NCOs, PLLs, and sample rates for the 73M1903 IC. The tables show some examples of the register settings for different clock and sample rates. A more detailed discussion on how these values are derived can be found in Appendix B.
3.1.1
Bit 7 Pseq7
Control Register (CTRL 8): Address 08h
Bit 6 Pseq6 Bit 5 Pseq5 Bit 4 Pseq4 Bit 3 Pseq3 Bit 2 Pseq2 Bit 1 Pseq1 Bit 0 Pseq0
Reset State 00h
This corresponds to the sequence of divisor. If Prst{2:0] =0 this register is ignored.
3.1.2
Bit 7 Prst2
Control Register (CTRL 9): Address 09h
Bit 6 Prst1 Bit 5 Prst0 Bit 4 Pdvsr4 Bit 3 Pdvsr3 Bit 2 Pdvsr2 Bit 1 Pdvsr1 Bit 0 Pdvsr0
Reset State 0Ah
Prst[2:0] represents the rate at which the sequence register is reset. Pdvsr[4:0] represents the divisor.
3.1.3
Bit 7 Ichp3
Control Register (CTRL 10): Address 0Ah
Bit 6 Ichp2 Bit 5 Ichp1 Bit 4 Ichp0 Bit 3 FL Bit 2 Kvco2 Bit 1 Kvco1 Bit 0 Kvco0
Reset State 22h
Kvco2:0 represents the magnitude of Kvco associated with the VCO within PLL. This indicates the center frequency of the VCO when the control voltage is 1.6 Volts and the slope of the VCO freq versus control voltage (i.e., Kvco.). FL represents the PLL loop filter settings. Table 4: Kvco versus Settings at Vc=1.6 V, 25 C Kvco2 0 0 0 0 1 1 1 1 Kvco1 0 0 1 1 0 0 1 1 Kvco0 0 1 0 1 0 1 0 1 Fvco 33 MHz 36 MHz 44 MHz 48 MHz 57 MHz 61 MHz 69 MHz 73 MHz Kvco 38 MHz/v 38 MHz/v 40 MHz/v 40 MHz/v 63 MHz/v 63 MHz/v 69 MHz/v 69 MHz/v
Rev. 2.0
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73M1903 Data Sheet Table 5: PLL Power Down Addr. 00h bit 7 ENFE 0 1 1 Addr. 0Eh bit 6 PwdnPLL X 0 1 PLL PLL Power Off PLL Power On PLL Power Off
DS_1903_032
Table 6: Examples of NCO Settings
PsDiv PllDiv Fs (kHz) Nnco1 Dnco1 PsSeq(7:0) PsRst =Dnco1 -1
7
Nnco2 Dnco2
PllSeq(7:0)
PllRst =Dnco2 -1
4
Fvco (Mhz)
PPM
7.2
8/125
15
11011010
5/96
19
XXX10000
33.177600
0
8.0 2.4*8/7*3 =8.22857142858 8.4 9.0 9.6 2.4*10/7*3 =10.2857142857 2.4*8/7*4 =10.9714285714 11.2* 12.0 12.8* 2.4*10/7*4 =13.7142857143 14.4 7.2 8.0 2.4*8/7*3 =8.22857142858 8.4 9.0 9.6 2.4*10/7*3 =10.2857142857 2.4*8/7*4 =10.9714285714 11.2 12 12.8 2.4*10/7*4 =13.7142857143 14.4 7.2 8.0 8.4 9.0 9.6 2.4*8/7*4 =10.9714285714 11.2 12
8/125 8/169 8/125 8/125 8/125 8/125 7/50 7/52 8/125 8/65 7/80 8/125 1/10 1/10 4/35 1/10 1/10 1/10 3/28 4/35 1/10 1/10 1/10 1/7 1/10 1/4 1/4 1/4 1/4 1/4 2/7 1/4 1/4
15 21 15 15 15 15 7 7 15 8 11 15 10 10 8 10 10 10 9 8 10 10 10 7 10 4 4 4 4 4 6 4 4
11011010 10000000 11011010 11011010 11011010 11011010 X1000000 X1010100 11011010 10000000 X1010100 11011010 XXXXXXXX XXXXXXXX XXXX1110 XXXXXXXX XXXXXXXX XXXXXXXX XXXXX100 XXXX1110 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX10 XXXXXXXX XXXXXXXX
7 7 7 7 7 7
3/64 3/89 5/112 1/24 5/128 7/192 8/107
21 29 22 24 25 27 13 14 32 17 26 38 13 15 13 15 16 18 18 18 21 22 24 18 27 14 16 16 18 19 19 22 24
XXXXX100 XXXXX110 XXX10100 XXXXXXXX XXX11010 X1010110 10100100 XXX10000 XXXXXXXX XXXX1110 XXXX1110 XXX10100 XXXXXX10 XXXXXXXX XXXXXX10 XXXX1110 11111110 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX10 XXXXXXXX XXXXXXXX XXXXXXXX XXX10100 XXXXXXXX XXX11110 XXXXXXXX XXX10000 XXX10000 XXX10100 XXXXXXXX
2 2 4 0 4 6 7 4 0 3 3 4 1 0 1 3 7 0 0 0 0 1 0 0 0 4 0 4 0 4 4 4 0
36.864000 37.917160* 38.707200 41.472000 44.236800 47.396571 50.557500* 51.611538* 55.296000 58.984615* 63.196875* 66.355200 33.177600 36.864000 37.917257... 38.707200 41.472000 44.236800 47.3965714.. 50.5563429.. 51.609600 55.296000 58.982400 63.19542... 66.355200 33.177600 36.864000 38.707200 41.472000 44.236800 50.556343 51.609600 55.296000
0 -3 0 0 0 0 23 38 0 38 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fxtal(Mhz)=27.0
6 6 7 7 6 7 0 0 3 0 0 0 2 3 0 0 0 0 0 0 0 0 0 0 4 0 0
5/71 1/32 4/71 4/107 5/192 2/27 1/15 2/27 4/63 8/135 1/18 1/18 1/18 1/21 2/45 1/24 1/18 1/27 5/72 1/16 5/84 1/18 5/96 5/96 5/112 1/24
Fxtal(Mhz)=9.216
Fxtal(Mhz)=24.576
14
Rev. 2.0
DS_1903_032
73M1903 Data Sheet
PsDiv
Fxtal(Mhz)= 25.35
12.8 14.4 7.2 8.0 2.4*8/7*3 =8.22857142858 8.4 9.0 9.6 2.4*10/7*3 =10.2857142857 2.4*8/7*4 =10.9714285714 11.2 12.0 12.8 2.4*10/7*4 =13.7142857143 14.4 7.2
1/4 1/8 8/125 2/25 4/73 8/125 4/25 8/125 8/125 6/59 8/125 4/25 8/125 5/61 7/73 8/163
4 8 15 12 18 15 6 15 15 9 15 6 15 12 10 20
XXXXXXXX XXXXXXXX 11011010 XXXXXX10 XXXX1000 11011010 XXXX1000 11011010 11011010 XX111110 11011010 XXXX1000 11011010 XXX10000 X1010100 10010010
0 0 7 1 3 7 3 7 7 5 7 3 7 4 6 7
5/128 5/288 5/108 5/96 6/173 5/126 5/54 5/144 7/216 7/145 5/168 5/72 5/192 8/257 6/173 3/80
PllDiv
Fs (kHz)
Nnco1 Dnco1
PsSeq(7:0)
PsRst =Dnco1 -1
Nnco2 Dnco2
PllSeq(7:0)
PllRst =Dnco2 -1 4 4 4 4 5 4 4 4 6 6 4 4 4 7 5 2
Fvco (Mhz)
PPM
25 57 21 19 28 25 10 28 30 20 33 14 38 32 28 26
XXX11010 XXX11010 XXX11010 XXX10000 XX111110 XXX10000 XXX11110 XXX11110 X1111110 X1110110 XXX11010 XXX10100 XXX10100 10000000 XX111110 110
58.982400 66.355200 33.1776 36.864 37.91781* 38.7072 41.472 44.2368 47.39657 50.5569* 51.6096 55.296 58.9824 63.19672* 66.35616* 33.177914*
0 0 0 0 15 0 0 0 0 12 0 0 0 21 15 10
Fxtal(Mhz)=24.000
Table 7: Clock Generation Register Settings for Fxtal = 27 MHz Reg Address Fs (kHz) 7.2 8.0 Dh Ichp Kvco 8h 9h Ah Bh Ch * (A) [2:0] DA EF 20 13 10 C4 DA EF 31 15 04 C2 8 10 12 10 10 10 12 8 8 8 6 8 12 0 1 1 1 1 2 3 3 3 4 5 6 6
2.4*8/7*3 80 F5 41 1D 06 C2 =8.22857142858 8.4 9.0 9.6 DA EF 31 16 14 C4 DA EF 31 18 XX C0 DA EF 32 19 1A C4
2.4*10/7*3 DA EF 43 1B 54 C6 =10.2857142857 2.4*8/7*4 40 C7 23 0D A4 C7 =10.9714285714* 11.2* 12.0 12.8* 54 C7 23 0E 10 C4 DA EF 24 20 XX C0 80 E8 15 11 0E C3
2.4*10/7*4 54 CB 26 1A 0E C3 =13.7142857143 14.4 DA EF 46 26 14 C4
Rev. 2.0
15
73M1903 Data Sheet Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz Reg Address Fs (kHz) 7.2 8.0 Ichp Kvco 8h 9h Ah Bh Ch Dh* (A) [2:0] XX 0A 10 0D 02 C1 XX 0A 11 0F XX C0 6 6 6 8 8 8 8 8 8 6 6 6 8 0 1 1 1 1 2 3 3 3 4 5 6 6
DS_1903_032
2.4*8/7*3 0E 68 11 0D 02 C1 =8.22857142858 8.4 9.0 9.6 XX 0A 21 0F 0E C3 XX 0A 21 10 FE C7 XX 0A 22 12 XX C0
2.4*10/7*3 04 49 23 12 XX C0 =10.2857142857 2.4*8/7*4 0E 68 23 12 XX C0 =10.9714285714 11.2 12 12.8 XX 0A 23 15 XX C0 XX 0A 14 16 02 C1 XX 0A 15 18 XX C0
2.4*10/7*4 XX 07 16 12 XX C0 =13.7142857143 14.4 XX 0A 26 1B XX C0
Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz Reg Address Fs (kHz) 7.2 8.0 8.4 9.0 9.6 Ichp Kvco 8h 9h Ah Bh Ch Dh* (A) [2:0] XX 04 20 0E 14 C4 8 0 1 1 1 2 3 3 4 5 6 XX 04 31 10 XX C0 10 XX 04 31 10 1E C4 10 XX 04 31 12 XX C0 10 XX 04 32 13 10 C4 10
2.4*8/7*4 02 23 33 13 10 C4 10 =10.9714285714 11.2 12 12.8 14.4 XX 04 33 16 14 C4 10 XX 04 24 18 XX C0 8 XX 04 35 19 1A C4 10 XX 08 66 39 1A C4 16
16
Rev. 2.0
DS_1903_032
73M1903 Data Sheet Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz Reg Address Fs (kHz) 7.2 8.0 2.4*8/7*3 =8.22857142858 8.4 9.0 9.6 2.4*10/7*3 =10.2857142857 2.4*8/7*4 =10.9714285714 11.2 12 12.8 2.4*10/7*4 =13.7142857143 14.4 8h DA 02 08 DA 08 DA DA 3E DA 08 DA 10 54 9h EF 2C 72 EF 66 EF EF A9 EF 66 EF 8C CA Ah Bh Ch Dh* 30 15 1A C4 31 13 10 C4 41 1C 3E C5 41 19 10 C4 11 0A 1E C4 42 1C 1E C4 43 1E 7E C6 33 14 76 C6 53 21 1A C4 14 0E 14 C4 45 26 14 C4 46 20 80 C7 46 1C 3E C5 Ichp (A) 10 10 12 12 6 12 12 10 14 6 12 12 12 Kvco [2:0] 0 1 1 1 1 2 3 3 3 4 5 6 6
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz Reg Address FS (KHz) 7.2 8h 92 9h F4 Ah Bh Ch Dh* 50 1A 06 C2 Ichp (A) 14 Kvco [2:0] 0
FrcVco 0 System Clock
Mux
1 2 Loop Filter Control VCO Locked Xtal Oscillator NCO Prescaler Fxtal Up Fref PFD Kd Dn Ichp Control 2 Kvco Control NCO 2 Charge Pump R1 C1 C2 VCO Kvco
Fvco
Figure 5: Clock Generation Rev. 2.0 17
73M1903 Data Sheet
DS_1903_032
4 Modem Receiver
A differential receive signal applied at the RXAP and RXAN pins or the output signal at TXAP and TXAN pass through a multiplexer, which selects the inputs to the ADC. In normal mode, RXAP/RXAN are selected. In analog loopback mode, TXAP/TXAN are selected. The DC bias for the RXAP/RXAN inputs is supplied from TXAP/TXAN through the external DAA in normal conditions. (See Appendix A) It can be supplied internally, in the absence of the external DAA, by setting RXPULL bit in Control Register 2. The output of the multiplexer goes into a second-order continuous time, Sallen-Key, low-pass filter (AAF) with a 3 dB point at approximately 40 kHz. The filtered output signal is the input to an analog sigma-delta modulator (ASDM), clocked at an over sampling frequency of 1.536 MHz for Fs = 8 kHz, which converts the analog signal to a serial bit stream with a pulse density that is proportional to the amplitude of the analog input signal. There are three gain control bits for the receive path. The RXGAIN bit in control register one results in a +20 dB gain of the receive signal when set to a "1". This 20 dB of gain compensates for the loss through the DAA while on hook. It is used for Caller ID reception. This gain is realized in the front end of ASDM. The other gain bits in control register 1, RXG1:0, compensate for differences in loss through the receive path. Table 12: Receive Gain RXG1 0 0 1 1 RXG0 0 1 0 1 Receive Gain Setting 6 dB 9 dB 12 dB 0 dB
The output of ASDM is a serial bit stream that feeds three digital sinc3 filters. Each filter has a [sin(x)/x]3 frequency response and provides a 16 bit sample every 288 clock cycles. The filters are synchronized so that there is one sample available after every 96 analog samples or at a rate of 16 kHz for Fs=8 kHz. The output of the sinc3 filter is a 17 bit, two's compliment number representing the amplitude of the input signal. The sinc3 filter, by virtue of holding action (for 96 sample period), introduces a droop in the passband that is later corrected for by a 48 tap FIR filter that follows. The maximum digital word that can be output from the filter is 0d800h. The minimum word is 12800h. The output of the sinc3 filter is input to another 48 tap digital FIR filter that provides an amplitude correction in the passband to the output of the sinc3 filter as well as rejecting noise above Fs/2 or 4 kHz for Fs=8 kHz. The output of this filter is then decimated by a factor of 2; so, the final output is 16 bit, two's compliment samples at a rate of 8 kHz. Figure 6 and Figure 7 depict the sinc3 filter's frequency response of ASDM along with the 48 tap digital FIR response that compensates for it and the resulting overall response of the receiver.
18
Rev. 2.0
DS_1903_032
73M1903 Data Sheet
Figure 6: Overall Receiver Frequency Response
Figure 7: Rx Passband Response It is important to keep in mind that the receive signal should not exceed 1.16 Vpk-diff for proper performance for Rxg=11 (0 dB). In particular, if the input level exceeds a value such that one's density of RBS exceeds 99.5%, sinc3 filter output will exceed the maximum input range of the decimation filter and consequently the data will be corrupted. Also for stability reasons, the receive signal should not exceed 1.16 Vpk differentially. This value is set at around 65% of the full receive signal of 1.791 Vpkdiff at RXAP/RXAN pins that "would" corresponds to ASDM putting out all ones. Figure 8 and Figure 9 show the spectrum of 1 kHz tone received at RXAP/RXAN of 1.16 Vpk-diff and 0.5 kHz and 1.0 kHz tones of 0.6 Vpk-diff each, respectively for Fs=8 kHz. Note the effect of FIR suppressing the noise above 4 kHz but at the same time enhancing (in order to compensate for the passband droop of sinc3 filter) it near the passband edge of 4 kHz. Rev. 2.0 19
73M1903 Data Sheet
DS_1903_032
Figure 8: RXD Spectrum of 1 kHz Tone
Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes
20
Rev. 2.0
DS_1903_032
73M1903 Data Sheet
5 Modem Transmitter
The modem transmitter begins with an 48 tap Transmit Interpolation Filter (TIF) that takes in the 16-bit, two's compliment numbers (TXD) at SDIN pin at Fs=8 kHz rate. It up-samples (interpolates) the data to 16 kHz rate rejecting the images at multiples of 8 kHz that exist in the original TXD data stream and outputs 16-bit, two's compliment numbers to a digital sigma-delta modulator. The gain of the interpolation filter is 0.640625 (-3.8679 dB) at DC. The digital sigma-delta modulator (DSDM) takes 16-bit, two's compliment numbers as input and generates a 1's bit stream which feeds into a D to A converter (DAC1). The gain through DSDM is 1.0. DSDM takes 16-bit, two's compliment numbers as input and generates a 1's bit stream that feeds into a D to A converter (DAC1). DAC1 consists of a 5-tap FIR filter and a first order switched capacitor low pass filter both operating at 1.536 MHz. It possesses nulls at multiples of 384 kHz to allow decimation by the succeeding filter. DAC1's differential output is fed to a 3rd-order switched-capacitor low pass filter (TLPF). The output of TLPF drives a continuous time smoothing filter. The sampling nature of the transmitter leads to an additional filter response that affects the in-band signals. The response is in the form of sin(x)/x and can be expressed as 20*log [(sin(PI*f/fs))/(PI*f/fs)] where f = signal frequency and fs = sample frequency = 16 kHz. Figure 10 shows the frequency response of the transmit path from TXD to TXAP/TXAN for a dc to 4 kHz in-band signal including the effect of this sampling process plus those of DAC1, TLPF and SMFLT. It is important to note that as TXD is sampled at 8 kHz, it be band-limited to 4 kHz.
Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal
Rev. 2.0
21
73M1903 Data Sheet
DS_1903_032
5.1
Transmit Levels
The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF) has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will result in a 0.5 (-6 dB) gain change in the analog output signal. The following formula describes the relationship between the transmit code word and the output level at the transmit pins (TXAP/TXAN): Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr Vout is the differential peak voltage at the TXAP and TXAN pins. Code is the 16-bit, two's compliment transmit code word written out by the DSP to the DSDM (via TIF). The code word falls within a range of 32,767. For a sinusoidal waveform, the peak code word should be used in the formula to obtain the peak output voltage. DSDMgain is the scaling factor used on the transmit code word to reduce the possibility of saturating the modulator. This value is set to 0.640625(-3.555821 dB) at dc in the 48 tap transmit interpolation filter (TIF) that precedes DSDM. dacGAIN is the gain of the DAC. The value dacGAIN is calculated based on capacitor values inside DAC1 and dacGAIN=8/9=0.8889. The number 32,767 refers to the code word that generates an 82% "1's" pulse density at the output of the DSDM. As one can see from the formula, the D to A conversion is dependent on the level of VREF. Also when TXBST1 bit is set, VREF is increased from 1.36 V to 1.586 V to allow higher transmit level or 16.6% increase in gain. This bit is intended for enhancing the DTMF transmit level and should not be used in data mode. TLPFgain is the gain of TLPF and nominally equals to 0.00 dB or 1.0. SMFLTgain is the gain of SMFLT and nominally equal to 1.445 or 3.2 dB. When TXBST0 bit is set, the gain is further increased by 1.65 dB (1.21) for the total of 4.85 dB. This is to accommodate greater hybrid insertion loss encountered in some applications. FreqFctr shows dependency of the entire transmit path on frequency. See Figure 10. With the transmit code word of +/- 32,767, the nominal differential swing at the transmit pins at dc is: Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr = 2 * 32,767/32767 * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.0 = 2.31Vpk diff. When TXBST1 bit is set, Vout (V) = 1.166 * 2.31= 2.693 Vpk diff. When TXBST0 bit is set, Vout (V) = 1.21 * 2.31= 2.795 Vpk diff, if not limited by power supply or internal reference. When both TXBST1 and TXBST0 are set to 1, Vout (V) = 1.166 * 1.21 * 2.31 = 3.259 Vpk diff.
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Rev. 2.0
DS_1903_032
73M1903 Data Sheet
5.2
Transmit Power - dBm
To calculate the analog output power, the peak voltage must be calculated and the peak to rms ratio (crest factor) must be known. The following formula can be used to calculate the output power, in dBm referenced to 600 . Pout (dBm) = 10 * log [ ( Vout (V) / cf )2 / ( 0.001 * 600 ) ] The following example demonstrates the calculation of the analog output power given a 1.2 kHz FSK tone (sine wave) with a peak code word value of 11,878 sent out by the DSP. The differential output voltage at TXAP-TXAN will be: With FreqFctr = 1.02, (See Figure 10) Vout (V) = 2 * (11,878/32,767) * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.02 = 0.841 V pk . The output signal power will be: Pout (dBm) = 10 * log [(0.841 / 1.41)2 / (0.001 * 600) ] = - 2.29 dBm. Table 13: Peak to RMS Ratios for Various Modulation Types Transmit Type V.90 QAM DPSK FSK DTMF Crest Factor 4.0 2.31 1.81 1.41 1.99 Max Line Level -12 dBm -9 dBm -9 dBm -9 dBm -5.7 dBm
5.3
Bit 7 ENFE ENFE
Control Register (CTRL1): Address 00h
Bit 6 Unused Bit 5 TXBST1 Bit 4 TXBST0 Bit 3 TXDIS Bit 2 RXG1 Bit 1 RXG0 Bit 0 RXGAIN
Reset State 08h
1 = Enable the digital filters and analog front end. 0 = Disable the analog blocks shut off the clocks to the digital and analog receive/transmit circuits. 1 = Add a gain of 1.335 dB (16.6%) to the transmitter; also the common mode voltage of the transmit path is increased to 1.375 V. This is intended for enhancing DTMF transmit power only and should not be used in data mode. 0 = No gain is added 1 = A gain of 1.65 dB (21%) is added to the transmitter 0 = The gain of the transmitter is nominal 1 = Tri-state the TXAP and TXAN pins, provides a bias of VBG into 80 k for each output pin These bits control the receive gain as shown in Table 12. 1 = Increase the gain of the receiver by 20 dB.
TXBST1
TXBST0
TXDIS RXG1:0 RXGAIN
Rev. 2.0
23
73M1903 Data Sheet
DS_1903_032
5.4
Bit 7 TMEN TMEN
Control Register (CTRL2): Address 01h
Bit 6 DIGLB Bit 5 ANALB Bit 4 INTLB Bit 3 CkoutEn Bit 2 RXPULL Bit 1 SPOS Bit 0 HC
Reset State 00h
1 = Enable test modes. 1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter input. DIGITAL LOOPBACK 1 = Tie the analog output of the transmitter to the analog input of the receiver. ANALOG LOOPBACK 1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter input. INTERNAL LOOPBACK 1 = Enable the CLKOUT output; 0 = CLKOUT tri-stated. For test purposes only; do not use in normal operation. 1 = Pulls DC Bias to RXAP/RXAN pins, through 100 k each, to VREF, to be used in testing Rx path. 0 = No DC Bias to RXAP/RXAN pins. 1 = Control frames occur after one quarter of the time between data frames has elapsed. 0 = Control frames occur half way between data frames. 1 = FS is under hardware control, bit 0 of data frames on SDIN is bit 0 of the transmit word and control frames happen automatically after every data frame. 0 = FS is under software control, bit 0 of data frames on SDIN is a control frame request bit and control frames happen only on request.
DIGLB
ANALB
INTLB
CkoutEn
RXPULL
SPOS
HC
5.5
Bit 7 Rev3
Revision Register: Address 06h
Bit 6 Rev2 Bit 5 Rev1 Bit 4 Rev0 Bit 3 Unused Bit 2 Bit 1 Bit 0
Reset State 30h Reserved Reserved Reserved
Bits 7-4 contain the revision level of the 73M1903 device. The rest of this register is for chip development purposes only and is not intended for customer use. Do not write to shaded locations.
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Rev. 2.0
DS_1903_032
73M1903 Data Sheet
6
Test Modes
There are two loop back test modes that affect the configuration of the analog front end. The internal loop back mode connects the serial bit stream generated by the analog receiver to the input of the analog transmitter. This loop back mode is similar to a remote analog loop back mode and can be used to evaluate the operation of the analog circuits. When using this loop back mode, the TXAN/TXAP pins should not be externally coupled to the RXAP/RXAN pins. Set bit 4 (INTLB) in register 1h (CTRL2) to enter this loop back mode. The second loop back test mode is the external loop back mode, or local analog loop back mode. In this mode, the analog transmitter outputs are fed back into the input of the analog receiver. Set bit 5 (ANALB) in register 1h (CTRL2) to enter this loop back mode. In this mode, TBS must be kept to below a value that corresponds to less than 1.16 V/2.31 V x -6 dB = 25% of the full scale code of +/- 32768 at TXD in order to ensure that the receiver is not overdriven beyond the maximum of 1.16 Vpkpk diff for Rxg=11(0 dB) setting. See Table 18 for the maximum allowed transmit levels. Check the transmitted data against received data via serial interface. This tests the functionality of essentially all blocks, both digital and analog, of the chip. There is a third loopback mode that bypasses the analog circuits entirely. Digital loop back forces the 3 transmitter digital serial bit stream (from DSDM) to be routed into the digital receiver's sinc filters. Set bit 6 (DIGLB) in register 1h (CTRL2) to enter this loop back mode.
7
Power Saving Modes
The 73M1903 has only one power conservation mode. When the ENFE, bit 7 in register 0h, is zero the clocks to the filters and the analog are turned off. The transmit pins output a nominal 80 k impedance. The clock to the serial port is running and the GPIO and other registers can be read or updated.
Rev. 2.0
25
73M1903 Data Sheet
DS_1903_032
8 Electrical Specifications
8.1 Absolute Maximum Ratings
Operation above maximum rating may permanently damage the device. Parameter Supply Voltage Pin Input Voltage (except OSCIN) Pin Input Voltage (OSCIN) Rating -0.5 V to +4.0 V -0.5 V to 6.0 V -0.5 V to VDD + 0.5 V
8.2
Recommended Operating Conditions
Rating 3.0 V to 3.6 V 24.576 MHz 100ppm -40 C to +85 C
Parameter Supply Voltage (VDD) with respect to VSS Oscillator Frequency Operating Temperature
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Rev. 2.0
DS_1903_032
73M1903 Data Sheet
8.3
8.3.1
Digital Specifications
DC Characteristics
Symbol VIL VIH1 VIH2 VOL IOL = 4 mA Conditions Min -0.5 0.7 VDD 0.7 VDD Nom Max 0.2 * VDD 5.5 VDD + 5.5 0.45 Unit V V V V
Parameter Input Low Voltage Input High Voltage (Except OSCIN) Input High Voltage OSCIN Output Low Voltage (Except OSCOUT, FS, SCLK, SDOUT) Output Low Voltage OSCOUT Output Low Voltage FS,SCLK,SDOUT Output High Voltage (Except OSCOUT, FS, SCLK, SDOUT) Output High Voltage OSCOUT Output High Voltage FS, SCLK, SDOUT Input Low Leakage Current (Except OSCIN) Input High Leakage Current (Except OSCIN) Input Low Leakage Current OSCIN Input High Leakage Current OSCIN
VOLOSC VOL VOH
IOL = 3.0 mA IOL = 1 mA IOH = -4 mA VDD - 0.45
0.7 0.45
V V V
VOHOSC VOH IIL1
IOH = -3.0 mA IOH = -1 mA VSS < Vin < VIL1
VDD - 0.9 VDD - 0.45 1
V V A
VIH1 < Vin < 5.5 IIH1 IIL2 VSS < Vin < VIL2 1
1
A
30
A
IIH2
VIH2 < Vin 1
30
A
IDD current at 3.0V - 3.6V Nominal at 3.3V
IDD Total current IDD Total current IDD Total current IDD Total current ENFE=0 IDD IDD IDD IDD Fs=8 kHz, Xtal=27 MHz Fs=11.2 kHz, Xtal=27 MHz Fs=14.4 kHz, Xtal=27 MHz 9 10.3 11.8 2 12.0 13.4 14.5 2.5 mA mA mA mA
Rev. 2.0
27
73M1903 Data Sheet
DS_1903_032
8.3.2
AC Timing
Table 14: Serial I/F Timing
Parameter SCLK Period (Tsclk) (Fs=8 kHz) SCLK to FS Delay (td1) - mode1 SCLK to FS Delay (td2) - mode1 SCLK to SDOUT Delay (td3) (With 10pf load) Setup Time SDIN to SCLK (tsu) Hold Time SDIN to SCLK (th) SCLK to FS Delay (td4) - mode0 SCLK to FS Delay (td5) - mode0
Min - - - - 15 10 - -
Nom 1/2.048 MHz - - - - - - -
Max - 20 20 20 - - 20 20
Unit ns ns ns ns ns ns ns ns
td1
td2 Tsclk
SCLK
FS (mode1)
SDOut
RX15 td3 tsu
RX14
RX1
RX0
SDIN
TX15 th
TX14
TX1
TX0
FS (mode0)
td4
td5
Figure 11: Serial Port Data Timing
28
Rev. 2.0
DS_1903_032
73M1903 Data Sheet
8.4
8.4.1
Analog Specifications
DC Specifications
VREF should be connected to an external bypass capacitor with a minimum value of 0.1 F. This pin is not intended for any other external use. Table 15: Reference Voltage Specifications Parameter VREF VREF Noise VREF PSRR Test Condition VDD= 3.0 V - 3.6 V. 300Hz-3.3 kHz 300Hz-30 kHz 40* Min Nom 1.36 -86 -80 Max Units V dBm 600 dB
8.4.2
AC Specifications
Table 16 shows the maximum transmit levels that the output drivers can deliver before distortion through the DAA starts to become significant. The loss though the DAA transmit path is assumed to be 7 dB. The signals presented at TXAP and TXAN are symmetrical. The transmit levels can be increased by setting either TXBST0 (+1.5 dB) or/and TXBST1 (+0.83 dB) for the combined total gain of 2.33 dB. These can be used where higher-level DTMF tones are required. Table 16: Maximum Transmit Levels
Transmit Type Maximum Different Line Level (dBm0) Maximum SingleEnded Level at TXA Pins (dBm) Peak to rms Ratio Single-Ended Single-Ended rms Voltage at Peak Voltage TXA Pins (V) at TXA Pins (v)
VPA=2.7 V to 3.6 V. All rms and peak voltages are relative to VREF. V.90 QAM DPSK FSK DTMF (high tone) DTMF (low tone) -12.0 -7.3 -5.1 -3.0 -7.8 -9.8 -11.0 -6.3 -4.1 -2.0 -6.8 -8.8 4 2.31 1.81 1.41 1.41 1.41 0.2175 0.377 0.481 0.616 0.354 0.283 0.87 0.87 0.87 0.87 0.500 0.400
Rev. 2.0
29
73M1903 Data Sheet
DS_1903_032
8.5
8.5.1
Performance
Receiver
Table 17: Receiver Performance Specifications Parameter Test Conditions Measured at RXAP/N relative to VREF RXPULL=HI Measured at RXAP/N relative to VREF RXPULL=LO 1.0 Min Nom 230 Max Units k M
Input Impedance
Receive Gain Boost
Rxgain = 1; 1 kHz; RXAP/N=0.116 V pk-diff Gain Measured relative to Rxgain=0 RXGAIN=1 for Fs=8 kHz RXGAIN =1 for Fs=12 kHz RXGAIN =1 for Fs=14.4 kHz THD = 2nd and 3rd harmonic. RXGAIN =1 Gain Measured relative to RXG[1:0]=11 (0 dB) @1 kHz RXG[1:0]=00 RXG[1:0]=01 RXG[1:0]=10 Input 1.16 V pk-diff at RXA. Measure gain at 0.5 kHz, and 2 kHz. Normalized to 1 kHz. Gain at 0.5 kHz Gain at 1 kHz (Normalized) Gain at 2.0 kHz Short RXAP to RXAN. Measure input voltage relative to VREF Normalized to VBG=1.25 V. Includes the effect of AAF(-0.4 dB) with Bits 1, 0 of CTRL2 register (01h) = 00. Peak voltage measured differentially across RXAP/RXAN.
17.0 16.2 15.7 64
18.5 17.4 17.2 70
20.0 18.7 18.7
dB dB dB
Total Harmonic Distortion (THD) RXG Gain
5.8 8.8 11.8
6 9 12
6.2 9.2 12.2
dB dB dB
Passband Gain
-0.29 -0.067 -30
-0.042 0.000 0.183 0
0.21 0.43 30
dB dB dB mV
Input offset
Sigma-Delta ADC Modulation gain Maximum Analog Signal Level at RXAP/RXAN Total Harmonic Distortion (THD) Noise Crosstalk
41
V/bit
1.16 1 kHz 1.16 V pk-diff at RXA with Rxg=11 THD = 2nd and 3rd harmonic. 80 Transmit V.22bis low band; FFT run on ADC samples. Noise in 0 to 4 kHz band 0 dBm 1000Hz sine wave at TXAP; FFT on Rx ADC samples, 1st four harmonics Reflected back to receiver inputs. 85 -85 -80
V pk-diff
dB dBm
-100
dB
Note: RXG[1:0] and RXGAIN are assumed to have settings of `0' unless they are specified otherwise.
30
Rev. 2.0
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73M1903 Data Sheet
8.5.2
Transmitter
Table 18: Transmitter Performance Specifications
Parameter DAC gain (Transmit Path Gain)
Test Condition Code word of 32,767 @1 kHz; TXBST0=0; TXBST1=0
Min
Nom 70
Max
Units v/bit
DC offset -Differential Across TXAP and TXAN for Mode DAC input = 0 DC offset -Common Mode TXBST0 Gain TXBST1 Gain Total Harmonic Distortion (THD) Average of TXAP and TXAN for DAC input = 0; relative to VREF Code word of 32,767 @1 kHz; relative to TXBST0=0; TXBST1=0 Code word of 32,767 @1 kHz; relative to TXBST0=0; TXBST1=0 Code word of 32,767 @1 kHz; relative to TXBST0=0;TXBST1=0 THD = 2nd and 3rd harmonic. Code word of ( 32,767*0.8) @1 kHz; relative to TXBST0=0;TXBST1=0 THD = 2nd and 3rd harmonic. 1200 Resistor across TNAN/TXAP Code word of ( 32,767*0.9) @1 kHz; relative to TXBST0=1;TXBST1=1 THD = 2nd and 3rd harmonic. Code word of 32,767 @1 kHz; relative to TXBST0=1;TXBST1=1 THD = 2nd and 3rd harmonic At output (TXAP-TXAN): DTMF 1.0 kHz, 1.2 kHz sine waves, summed 2.0 V pk (-2 dBm tone summed with 0 dBm tone) Refer to TBR 21 specifications for description of complete requirements. 200 Hz - 4.0 kHz -30 dBm signal at VPA 300 Hz - 30kHz 300 Hz - 3.2kHz Code word of 32,767 @1 kHz. Measure gain at 0.5 kHz, and 2 kHz relative to 1 kHz. Gain at 0.5 kHz Gain at 1 kHz (Normalized) Gain at 2.0 kHz Gain at 3.3 kHz
-100 -80 1.65 1.335
100 80
mV mV dB dB
-75
-85
dB
-80
-85
dB
-60
-70
dB
-70 dB below low tone V 40 -0.125 0.125 dB dB
Intermod Distortion
70
Idle Channel Noise PSRR Passband Ripple
110
Transmit Gain Flatness
0.17 0 0.193 -0.12
dB dB dB dB
Rev. 2.0
31
73M1903 Data Sheet
DS_1903_032
Parameter TXAP/N Output Impedance Differentially (TXDIS=1) TXAP/N Common Output Offset (TXDIS=1)
Test Condition TXDIS=1 Measure impedance differentially between TXAP and TXAN. TXDIS=1 Short TXAP and TXAN. Measure the voltage respect to Vbg.
Min
Nom 160
Max
Units k
-20
0
20
mV
Note: TXBST0 and DTMFBS are assumed to have setting 0's unless they are specified otherwise.
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Rev. 2.0
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73M1903 Data Sheet
9 Pinouts
9.1 32-Pin QFN Pinout
SDOUT SckMode
GPIO7
GPIO6
SDIN
TYPE
32
31
30
29
28
27
26
VND VPD GPIO0 GPIO1 GPIO2 GPIO3 FS SCLK
25
VPD
N/C
1 2 3 4 5 6 7 8
24 23 22
GPIO5 GPIO4 VND N/C VPPLL OSCIN OSCOUT VNPLL
TERIDIAN 73M1903
21 20 19 18 17
10
11
12
13
14
15 RXAP
RXAN
TXAN
TXAP
RST
Figure 12: 32-Pin QFN Pinout Table 19: 32-Pin QFN Pin Definitions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VND VPD GPIO0 GPIO1 GPIO2 GPIO3 FS SCLK RST VPA TXAN TXAP VREF RXAN RXAP VNA Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VNPLL OSCOUT OSCIN VPPLL CLKOUT VND GPIO4 GPIO5 VPD N/C TYPE SckMode SDIN GPIO6 GPIO7 SDOUT
Rev. 2.0
VREF
VPA
VNA
16
9
33
73M1903 Data Sheet
DS_1903_032
9.2
20-Pin TSSOP Pinout
SDOUT VND VPD FS SCLK VREF RST VPA TXAN TXAP
1 2 3 4 5 20 19 18 17 16
SDIN TYPE VND VPPLL OSCIN OSCOUT VNPLL VNA RXAP RXAN
73M1903
6 7 8 9 10 15 14 13 12 11
Figure 13: 20-Pin TSSOP Pinout Table 20: 20-Pin TSSOP Pin Definitions Pin 1 2 3 4 5 6 7 8 9 10 Name SDOUT VND VPD FS SCLK VREF RST VPA TXAN TXAP Pin 11 12 13 14 15 16 17 18 19 20 Name RXAN RXAP VNA VNPLL OSCOUT OSCIN VPPLL VND TYPE SDIN
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Rev. 2.0
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73M1903 Data Sheet
10 Mechanical Specifications
10.1 32-Pin QFN Mechanical Drawings
Dimensions in mm.
0.85 NOM./ 0.9MAX. 0.00 / 0.005 0.20 REF.
2.5
5
1 2 3
2.5 5
SEATING PLANE
SIDE VIEW
TOP VIEW
0.35 / 0.45
3.0 / 3.75 0.18 / 0.3 1.5 / 1.875
CHAMFERED 0.30
1 2 3
3.0 / 3.75
0.2 MIN. 0.35 / 0.45
Figure 14: 32-Pin QFN Mechanical Specifications
0.25 1.5 / 1.875 0.5
0.5 0.25
BOTTOM VIEW
Rev. 2.0
35
73M1903 Data Sheet
DS_1903_032
10.2 20-Pin TSSOP Mechanical Drawings
Dimensions in mm.
Figure 15: 20-Pin TSSOP Mechanical Specifications
36
Rev. 2.0
DS_1903_032
73M1903 Data Sheet
11 Ordering Information
Part Description 73M1903 32-Lead QFN Lead Free 73M1903 32-Lead QFN, Tape and Reel, Lead Free 73M1903 20-Lead TSSOP Lead Free 73M1903 20-Lead TSSOP, Tape and Reel, Lead Free Order Number 73M1903-IM/F 73M1903-IMR/F 73M1903-IVT/F 73M1903-IVTR/F Package Mark 73M1903-M 73M1903-M 73M190IVT 73M190IVT
Rev. 2.0
37
73M1903 Data Sheet
DS_1903_032
Appendix A - 73M1903 DAA Resistor Calculation Guide
The following procedure can be used to approximate the component values for the DAA. The optimal values will be somewhat different due to the effects of the reactive components in the DAA (this is a DC approximation). Simulations with the reactive components accurately modeled will yield optimal values. The procedures for calculating the component values in the DAA are as follows. First set up R1. The DAA should be designed to reflect 600 when looking in at TIP/RING. If the transformer is 1 to 1, the holding coil and ring detect circuit are high impedance, Cblock is a high value so in the frequency band of interest it is negligible, the sum of R2 and R3 is much greater than R1, and the output impedance of the drivers driving TXAP/TXAN are low then:
Rin 2 .R1 RW Rohswitch 2 .Rbead
RW is the sum of the winding resistance of both sides of the transformer. Measure each side of the transformer with an Ohmmeter and sum them. Rohswitch is the on resistance of the Off Hook Switch. Mechanical Relay switches can be ignored, but Solid State Relays sometimes have an appreciable on resistance. Rbead is the DC resistance of whatever series RF blocking devices may be in the design. For Rin equal to 600 :
R1 600 RW Rohswitch 2 2 .Rbead
To maximize THL (Trans-Hybrid Loss), or to minimize the amount of transmit signal that shows up back on the Receive pins. The RXAP/RXAN pins get their DC bias from the TXAP/TXAN pins. By capacitively coupling the R3 resistors with the C1 caps, the DC offset can be minimized from the TXAP/TXAN to the RXAP/RXAN because the DC offset will be divided by the ratio of the R1 resistors to the winding resistance on the one side of the transformer. Next make the sum of R2 + R3 much higher than 600 . Make sure they are lower than the input impedance of the RXAP/RXAN pins; otherwise they can move the frequency response of the input filter. So let R2 + R3 = 100K. 38 Rev. 2.0
DS_1903_032
73M1903 Data Sheet
R3 1
100 K Rwtot 1200 600
where
Rwtot RW Rohswitch R2 100 K R3 2 .Rbead
Use 1% resistors for R1, R2, and R3 To select the value for C1, make the zero at around 10Hz.
1 10 2 . .100 K .C1 1 C1 . .100 K .10 2
C1 0.15 uF
The blocking cap Cblock should also have the same frequency response, but due to the low impedance, its value will be much higher, usually requiring a polarized cap. A blocking cap may also be needed on the modem side of the transformer if the DC offset current of the transmit pins will exceed the current rating of the transformer.
1 . .600 .10 2 Cblock 27 uF Cblock
If you are using a Wet transformer design, as in the following figure:
The only difference is that the blocking capacitor, Cblock, it is removed. All other equations still hold true.
Rev. 2.0
39
73M1903 Data Sheet
DS_1903_032
Trans-Hybrid Loss (THL)
Trans-Hybrid Loss is by definition the loss of transmit signal from Tip/Ring to the receive inputs on the modem IC. This definition is only valid when driving a specific phone line impedance. In reality, phone line impedances are never perfect, so this definition isn't of much help. Instead, as an alternate definition that helps in analysis for this modem design, THL is the loss from the transmit pins to the receive pins. In this definition the worst-case THL from the transmit pins to the Receive pins is 10.8 dB. An insertion loss of 7 dB is assumed accounting for losses due to switch, bridge and transformer.
40
Rev. 2.0
DS_1903_032
73M1903 Data Sheet
Appendix B - Crystal Oscillator
The crystal oscillator is designed to operate over wide choice of crystals (from 9 MHz to 27 MHz). The crystal oscillator output is input to an NCO based pre-scaler (divider) prior to being passed onto an onchip PLL. The intent of the pre-scaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference frequency, Fref, for the PLL. A set of three numbers- Pdvsr (5 bit), Prst (3 bit) and Pseq (8 bit) must be entered through the serial port as follows: Pdvsr = Integer [Fref/Fxtal]; Prst = Denominator of the ratio (Fref/Fxtal) minus 1 when it is expressed as a ratio of two smallest integers = Nnco1/Dnco1; Pseq = Divide Sequence
Fxtal Pdvsr Pdvsr +1
Sequence Register
overflow
Fref
Counter
mux
count ctrl
Sequence Counter
Rst Pseq[7:0] Prst[2:0]
Figure 16: NCO Block Diagram Please note that in all cases, pre-scaler should be designed such that pre-scaler output frequency, Fref, is in the range of 2 ~ 4 MHz. In the first example below, the exact divide ratio required is Fxtal/Fref = 15.625 =125/8. If a divide sequence of {/16,/16,/15,/16,/16,/15,/16,/15} is repeated, the effective divide ratio would be exactly 15.625. Consequently, Pdvsr of 15, the length of the repeating pattern, Prst = 8 -1 =7, and the pattern, {1,1,0,1,1,0,1,0}, where 0 means Pdvsr, or /15, and 1 means Pdvsr +1, or /16 must be entered as below. Example 1: Fxtal = 27 MHz, Fref = 1.728 MHz. Pdvsr = Integer [Fxtal/Fref] = 15 =0Fh Prst[2:0] = 8 - 1 = 7 from Fxtal/Fref = 15.625 =125/8; Pseq = /16,/16,/15,/16,/16,/15,/16,/15 => {1,1,0,1,1,0,1,0} =DAh. In the second example, Fxtal/Fref =4.0. This is a constant divide by 4. Thus Pdvsr is 4, Prst = 1 -1 =0 and Pseq = {x,x,x,x,x,x,x,x).
Rev. 2.0
41
73M1903 Data Sheet Example 2: Fxtal = 18.432 MHz, Fref = 2.304 MHz. Pdvsr = Integer [Fxtal/Fref] = 8 = 8h; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 18.432/2.304 = 8/1; Pseq = {x,x,x,x,x,x,x,x} = xxh Example 3: Fxtal = 24.576 MHz, fref = 2.4576 MHz. Pdvsr = Integer [ Fxtal/Fref] = 10 = Ah; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/2.4576 = 10/1; Pseq = {x,x,x,x,x,x,x,x} = xxh
DS_1903_032
It is also important to note that when Fxtal/Fref is an integer the output of the pre-scaler is a straight frequency divider (example 2). As such there will be no jitter generated at Fref. However if Fxtal/Fref is a fractional number, Fref, at the output of the pre-scaler NCO would be exact only in an average sense (example 1) and there will be a certain amount of fixed pattern (repeating) jitter associated with Fref which can be filtered out by the PLL that follows by appropriately programming the PLL. It is important to note, however, that the fixed pattern jitter does not degrade the performance of the sigma delta modulators so long as its frequency is >> 4 kHz.
PLL
NCO Prescaler Up Fref PFD Kd Dn Ichp Control 3 Kvco Control NCO 3 Charge Pump R1 C1 C2 VCO Kvco Divide by 2/1
Figure 17: PLL Block Diagram 1903B has a built in PLL circuit to allow an operation over wide range of Fs. It is of a conventional design with the exception of an NCO based feedback divider. See Figure 17. The architecture of the 73m1903 dictates that the PLL output frequency, Fvco, be related to the sampling rate, fs, by fvco = 2 x 2304 x fs. The nco must function as a divider whose divide ratio equals Fref/Fvco. Just as in the NCO pre-scaler, a set of three numbers- Ndvsr (7 bits), Nrst (3 bit ) and Nseq (8 bits) must be entered through a serial port to effect this divide: Ndvsr = Integer [ Fref/Fxtal ] ; Nrst = denominator of the ratio (Fvco/Fref), Dnco1, minus 1, when it is expressed as a ratio of two smallest integers = Nnco1/Dnco1; Nseq = Divide Sequence Example 1: Fs = 7.2 kHz or Fvco = 2 x 2304 x 7.2 kHz =33.1776 MHz, Fref = 1.728 MHz. Ndvsr = Integer [ Fvco/Fref ] = 19 Nrst = 5 - 1 = 4 from Fvco/Fref = 19.2 = 96/5; Nseq = /19, /19, /19, /19, /20 => {0,0,0,0,1} =xxx00001 = 01h. 42 Rev. 2.0
DS_1903_032 Example 2: Fs = 8.0 kHz or Fvco = 2 x 2304 x 8 kHz =36.864 MHz, Fref = 2.304 MHz. Ndvsr = Integer [Fvco/Fref] = 16 = 10h; Nrst= 1-1 = 0 from Fvco/Fref = 16/1; Nseq = {x,x,x,x,x,x,x,x} = xxh. Example 3: Fs = 9.6 kHz or Fvco = 2 x 2304 x 9.6 kHz =44.2368 MHz, Fref = 2.4576 MHz. Ndvsr = Integer [Fvco/Fref] = 18 = 16h; Nrst= 1-1 = 0 from Fvco/Fref = 18/1; Nseq = {x,x,x,x,x,x,x,x} = xxh.
73M1903 Data Sheet
It is important to note that in general the NCO based feedback divider will generate a fixed jitter pattern whose frequency components are at Fref/Accreset2 and its integer multiples. The overall jitter frequency will be a nonlinear combination of jitters from both pre-scaler and PLL NCO. The fundamental frequency component of this jitter is at Fref/Prst/Nrst. The PLL parameters should be selected to remove this jitter. Three separate controls are provided to fine tune the PLL as shown in the following sections. To ensure quick settling of PLL, a feature was designed into the 73m1903 where Ichp is kept at a higher value until lokdet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus PLL is guaranteed to have the settling time of less than one frame synch period after a new set of NCO parameters had been written to the appropriate registers. The serial port register writes for a particular sample rate should be done in sequence starting from register 08h ending in register 0dh. 0dh register should be the last one to be written to. This will be followed by a write to the next register in sequence (0eh) to force the transition of Sysclk from Xtal to Pllclk. Upon the system reset, the system clock is reset to Fxtal/9. The system clock will remain at Fxtal/9 until the host forces the transition, but no sooner the second frame synch period after the write to 0dh. When this happens, the system clock will transition to pllclk without any glitches through a specially designed deglitch mux.
Examples of NCO Settings
Example 1: Crystal Frequency = 24.576 MHz; Desired Sampling Rate, Fs = 13.714 kHz(=2.4 kHz x 10/7 x 4) Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4 kHz x 10/7 x 4 = 13.714 kHz, or Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 10/7 x 4 = 63.19543 MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by:
Fvco / Fxtal
=
2 * 2304 * 2.4kHz * 10/7 * 4 24.576 MHz
.
After a few rounds of simplification this ratio reduces to:
Fvco / Fxtal = 18 7 Nnco1 Dnco1 Nnco2 Dnco2 =( 1 7 = )*( 1 7 1 18 18 1 )
=
Rev. 2.0
43
73M1903 Data Sheet
DS_1903_032
where Nnco1 and Nnco2 must be < or equal to 8. The ratio, Nnco1/Dnco1 = 1/7, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 = 1/18 for the NCO in the PLL. Prescaler NCO: From Nnco1/Dnco1 = 1/7, Pdvsr = Integer [ Dnco1/Nnco1 ] = 7; Prst[2:0] = Nnco1 - 1 = 0; this means NO fractional divide. It always does /7. Thus Pseq becomes "don't care" and is ignored. Pseq = {x,x,x,x,x,x,x,x} = xxh. PLL NCO: From Nnco2/Dnco2 = 1/18, Ndvsr = Integer [ Dnco2/Nnco2 ] = 18; Nrst[2:0] = Nnco2 - 1 = 0; this means NO fractional divide. It always does /18. Thus Pseq becomes "don't care" and is ignored. Nseq = {x,x,x,x,x,x,x,x} = xxh. Example 2: Crystal Frequency = 24.576 MHz; Desired Sampling Rate, Fs = 10.971 kHz=2.4 kHz x 8/7 x4 Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4 kHz x 8/7 x 4 =10.971 kHz. Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 8/7 x 4 = 50.55634 MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by:
Fvco / Fxtal
=
2 * 2304 * 2.4kHz * 8/7 * 4 24.576 MHz
.
After a few rounds of simplification this ratio reduces to: 4 18 Fvco / Fxtal = ( )*( ) 35 1 Nnco1 4 Dnco1 35 = = Nnco2 1 Dnco2 18 , where Nnco1 and Nnco2 must be < or equal to 8. The ratio, Nnco1/Dnco1 = 4/35, is used to form a divide ratio for the NCO in pre-scaler and Nnco2/Dnco2 =1/18 for the NCO in the PLL. Pre-scaler NCO: From Nnco1/Dnco1 = 4/35, Pdvsr = Integer [ Dnco1/Nnco1 ] = 8; Prst[2:0] = Nnco1 - 1 = 3; Dnco1/Nnco1 = 35/4 = 8.75 suggests a divide sequence of {/9,/9,/9,/8}, or Pseq = {x,x,x,x,1,1,1,0} = xDh. PLL NCO: From Nnco2/Dnco2 = 1/18, Ndvsr = Integer [ Dnco2/Nnco2 ] = 18; Nrst[2:0] = Nnco2 - 1 = 0; this means NO fractional divide. It always does /18. Thus Pseq becomes "don't care". Nseq = {x,x,x,x,x,x,x,x} = xxh. 44 Rev. 2.0
DS_1903_032 Example 3: Crystal Frequency = 27 MHz; Desired Sampling Rate, Fs = 7.2 kHz Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4 kHz x 3 = 7.2 kHz. Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 3 = 33.1776 MHz.
73M1903 Data Sheet
Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by:
Fvco / Fxtal
=
2 * 2304 * 2.4kHz * 3 27 MHz
.
After a few rounds of simplification this reduces to:
Fvco / Fxtal =( 8 125 Nnco1 Dnco1 Nnco2 Dnco2 )*( 96 5 = ) 8 125 5 96
=
The two ratios are not unique and many other possibilities exist. But for this particular application, they are found to be the best set of choices within the constraints of Prst and Nrst allowed. (Nnco1, Nnco2 must be less than or equal to 8.) The ratio, Nnco1/Dnco1 = 8/125, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 =5/96 for the NCO in the PLL. Pre-scaler NCO: From Nnco1/Dnco1 = 8/125, Pdvsr = Integer [ Dnco1/Nnco1 ] = 15; Prst[2:0] = Nnco1 - 1 = 7; Dnco1/Nnco1 = 125/8 = 15.625 suggests a divide sequence of {/16,/16,/15,/16,/16,/15,/16,/15}, or Pseq = {1,1,0,1,1,0,1,0} = DAh. PLL NCO: From Nnco2/Dnco2 = 5/96, Ndvsr = Integer [ Dnco2/Nnco2 ] = 19; Nrst[2:0] = Nnco2 - 1 = 4; Dnco2/Nnco2 = 19.2 suggests a divide sequence of {/19, /19, /19, /19, /20}, or Nseq = {x,x,x,0,0,0,0,1} = x1h.
Rev. 2.0
45
73M1903 Data Sheet
DS_1903_032
Revision History
Rev. # 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2.0 Date 4/16/2004 12/13/2004 7/15/2005 9/14/2006 9/14/2006 5/23/2007 12/14/2007 1/17/2008 2/23/2009 Comments First publication. Minor modification for format. Company logo change and minor modification for format. Corrected QFN pin-out drawing. Corrected QFN pin-out drawing. Added 20-VT package information. Changed 32-QFN from punched to SAWN. Removed the leaded package option. Changed the bottom view package dimension for 32-QFN package. Removed all references to the 32-pin TQFP package. Formatted to the new corporate standard.
(c) 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. MicroDAA is a registered trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com 46 Rev. 2.0

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